The present invention relates to an amplification type solid-state image pickup device.
Conventionally, there has been proposed an amplification type solid-state image pickup device having a pixel area, in which an amplification function is imparted to each pixel, and scanning circuits provided around the pixel area, where pixel data is read by the scanning circuits. Among others, there have been known an APS (Active Pixel Sensor) type image sensor composed of CMOS which is advantageous for integration of the pixel area with its surrounding drive circuit and signal processing circuit.
For the APS type image sensor, it is necessary to provide a photoelectric conversion part, an amplification part, a pixel selector part and a reset part within one pixel. Typically, the photoelectric conversion part is formed of a photodiode (PD), and the amplification part, the pixel selector part and the reset part are implemented by using three to four MOS transistors (Tr).
FIG. 5 shows a construction of an APS type image sensor which is of the PD+3Tr style with the use of one photodiode (PD) and three MOS transistors (Tr). This PD+3Tr style is disclosed in, for example, Mabuchi et al., “A ¼ Inch 330 k Pixel VGA CMOS Image Sensor” (Technical Report of the Institute of Image Information and Television Engineers, IPU'97-13, March, 1997).
Referring to FIG. 5, reference numeral 201 denotes an amplification-use MOS transistor, 202 denotes a reset-use MOS transistor, 203 denotes a pixel-selection-use MOS transistor, 204 denotes a photoelectric-conversion-use photodiode, 205 denotes a signal line, 206 denotes a power supply line, 207 denotes a pixel-selection clock line, and 280 denotes a reset clock line. The pixel-selection-use MOS transistor 203 is driven by a vertical scanning circuit 221 via the pixel-selection clock line 207. Also, the reset-use MOS transistor 202 is driven by a vertical scanning circuit 222 via the reset clock line 280. Further, a MOS transistor 230 (gate bias voltage: VG), which serves as a constant-current load, is connected to the signal line 205, where an output voltage of the signal line 205 is read to a horizontal signal line 236 via an amplifier (amplification-use MOS transistor) 231 and a MOS transistor 232. The MOS transistor 232 is driven by a horizontal scanning circuit 234 via a horizontal clock line 235. A MOS transistor 233 (gate bias voltage: VL2), which serves as a constant-current load, is connected to the horizontal signal line 236, and a voltage of the horizontal signal line 236 is amplified by an amplifier 237 so as to be outputted as a signal OS.
In the amplification type solid-state image pickup device shown in FIG. 5, assuming that the under-gate channel voltage for turn-on of the reset-use MOS transistor 202 is φRH and that the reset drain voltage is a power supply voltage VDD, and given thatVDD<φRH,then, as shown in FIG. 6, when the reset-use MOS transistor 202 is turned on, the voltage of the photodiode 204 is reset to the power supply voltage VDD. However, after the reset-use MOS transistor 202 has turned off, the photodiode 204 yields occurrence of reset noise ΔNrn expressed in electron numbers as:ΔNrn=(√{square root over (kTCp)})/q  (1)where k is Boltzmann's constant, T is an absolute temperature, Cp is a capacitance of the photodiode 204 and a region adjoining thereto, and q is the elementary  electric charge. As apparent from the above Equation (1), the reset noise ΔNrn depends on the capacitance Cp, and increases with increasing capacitance Cp. In the following description, resetting the voltage of the photodiode 204 by such a reset-use MOS transistor 202 is defined as a “hard reset opration.”
As apparent from FIG. 5, since the capacitance Cp includes, in addition to the capacitance of the photodiode 204 itself, the gate capacitance of the amplification-use MOS transistor 201 as well as an interconnecting capacitance of these, it is difficult to reduce the reset noise ΔNrn. That is, in the case of the construction of FIG. 5, the reset noise ΔNrn has been a large issue.
Therefore, as a method for reducing the reset noise as described above, there has been proposed a noise reduction method by a “soft reset operation” as shown below (Bedabrata Pain et al., Analysis and enhancement of low-light-level performance of photodiode-type CMOS active pixel imagers operated with sub-threshold reset, IEEE Workshop on CCDs and Advanced Image Sensors 1999, p.140).
FIG. 7 shows potential relations in the pixel area during this soft reset operation. Hereinbelow, the soft reset operation is explained with reference to FIG. 7. It is noted that the amplification type solid-state image pickup device in this case is similar in construction to the amplification type solid-state image pickup device of FIG. 5 except the operation timing.
Referring to FIG. 7, upon a turn-on of the reset-use MOS transistor 202, if the under-gate channel voltage φRH satisfies a relation thatφRH<VDD,then the voltage of the photodiode 204 is reset to a sub-threshold region around the under-gate channel voltage φRH. In this case, after the reset-use MOS transistor 202 is turned off, the photodiode 204 yields occurrence of soft reset noise ΔNsr expressed in electron numbers as:ΔNsr=(√{square root over (kTCp/2)})/q  (2)That is, in this soft reset operation, noise is reduced to √{square root over ((½))}=0.71 time that of the hard reset operation of the case of Equation (1), in terms of electron number.
However, in the case where the voltage of the drain of the reset-use MOS transistor 202 is fixed to the power supply voltage VDD in FIG. 7, since the voltage of the photodiode 204 is not fixed because of leaks due to the sub-threshold current at the gate of the reset-use MOS transistor 202, there is a problem that image retention would occur.
Therefore, in order to avoid this problem, it has been proposed to perform the hard reset operation before the soft reset operation. That is, before the soft reset operation, the reset drain voltage is once set to a voltage (VDD−Δφm) which is lower than the under-gate channel voltage φRH. As a result, since the voltage of the photodiode 204 is fixed to (VDD−Δφm), the voltage of the photodiode 204 shifted by leaks due to the sub-threshold current is fixedly set every store period, so that there would occur no image retention. A circuit diagram in this case is shown in FIG. 8, and its timing charts are shown in FIGS. 9A to 9H.
Referring to FIG. 8, reference numeral 301 denotes an amplification-use MOS transistor, 302 denotes a reset-use MOS transistor, 303 denotes a pixel-selection-use MOS transistor, 304 denotes a photoelectric-conversion-use photodiode, 305 denotes a signal line, 307 denotes a pixel-selection clock line, and 310 denotes a power supply line to which drains of the amplification-use MOS transistor 301 and the reset-use MOS transistor 302 are connected and which horizontally extends in units of rows of the pixel array. A reset drain voltage VP(i) is applied to the drain of the reset-use MOS transistor 302 via the power supply line 310. Also, reference numeral 380 denotes a reset clock line to which the gate of the reset-use MOS transistor 302 is connected and which horizontally extends in units of rows of the pixel array. A reset gate voltage RS(i) is applied to the gate of the reset-use MOS transistor 302 via the reset clock line 380.
The reset drain voltage VP(i) is changed between binary levels by MOS transistors 311, 312 and a pulse VPo(i). That is, when the pulse VPo(i) is at a Low level, the MOS transistor 311 is turned on, so that the reset drain voltage VP(i) becomesVP(i)=VDD.Meanwhile, when the pulse VPo(i) is at a High level, the MOS transistor 311 is turned off, so that the reset drain voltage VP(i) lowers from the power supply voltage VDD by a voltage drop Δφm of the MOS transistor 312, becomingVP(i)=VDD−Δφm,and the resulting reset drain voltage VP(i) is applied to the power supply line 310. Timings for these operations are shown in the timing charts of FIGS. 9A to 9H.
Referring to FIGS. 9A to 9H, in a reset period (T11+T12) during which the reset gate voltage RS(i) keeps at the High level, the reset drain voltage VP(i) in its first half period T11 becomesVP(i)=VDD−Δφm,where ensuring thatVDD−Δφm<φRHallows the voltage of the photodiode 304 to be fixed to (VDD−Δφm). That is, the hard reset operation is performed.
Next, in the second half period T12, the reset drain voltage VP(i) becomes the power supply voltage VDD, where setting the under-gate channel voltage φRHφRH<VDDallows the soft reset operation to be performed.
However, with the noise reduction method of the “hard reset operation to soft reset operation” type shown in FIGS. 8 and 9A to 9H, although image retention is avoided, yet the reset noise is reduced only to at most 0.71 time that of the normal hard reset operation, in terms of electron numbers, as shown in Equation (2), which is an insufficient level for image sensors of high image quality.
Accordingly, an object of the present invention is to provide an amplification type solid-state image pickup device capable of greatly reducing the reset noise with an extremely simple construction.